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PI6C2516
Phase-Locked Loop Clock Driver with 16 Clock Outputs
Product Features
High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications. Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank. Allow Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation. Maximum clock frequency of 150 MHz. Low jitter: Cycle-to-Cycle jitter 100ps max Operates at 3.3V VCC Available Packaging: 48-pin TSSOP (Thin Shrink Small Outline) (A)
Description
The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any clock output will be nearly zero. This zero-delay feature allows the CLK input clock to be distributed, providing 4 banks of four outputs. For test purposes, the PLL can be bypassed by strapping the AVCC to ground. The PI6C2516 family has the same pinout as the TI CDC2516, with the added feature of allowing Spread Spectrum clock input.
Pin Description
VCC 1Y0 1Y1 GND GND 1Y2 1Y3 VCC 1G GND AVCC CLK AGND AGND GND 2G VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 48-Pin 39 11 A 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC 4Y0 4Y1 GND GND 4Y2 4Y3 VCC 4G GND AVCC FB_IN AGND FB_OUT GND 3G VCC 3Y0 3Y1 GND GND 3Y2 3Y3 VCC
Block Diagram
1G 2G 3G 4G
4 4 4
1Y [0:3] 2Y [0:3] 3Y [0:3]
CLK PLL FB_IN AVCC
4
4Y [0:3] FB_OUT
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PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs
Pin Functions
Pin Name CLK FB_IN Pin Numbe r 12 37 Type I I D e s cription Clock input. CLK allows spread spectrum. Feedback input. FB_IN provides the feedback signal to the internal PLL. CLK and FB_IN are synchronized so that there is normally zero phase error between CLK and FB_IN. O utput bank enable. When 1G is LO W, outputs 1Y[0:3] are disabled to a logic low state. When 1G is HIGH, all outputs 1Y[0:3] are enabled and switched at the same frequency as CLK . O utput bank enable. When 2G is LO W, outputs 2Y[0:3] are disabled to a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled and switched at the same frequency as CLK . O utput bank enable. When 3G is LO W, outputs 3Y[0:3] are disabled to a logic low state. When 3G is HIGH, all outputs 3Y[0:3] are enabled and switched at the same frequency as CLK . O utput bank enable. When 4G is LO W, outputs 4Y[0:3] are disabled to a logic low state. When 4G is HIGH, all outputs 4Y[0:3] are enabled and switched at the same frequency as CLK . Feedback output. FB_O UT is dedicated for external feedback. FB_O UT has an embedded 25 series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25 series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25 series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25 series- damping resistor of the same value as the clock outputs. Clock outputs. These outputs provide low- skew copies of CLK _IN. Each output has an embedded 25 series- damping resistor of the same value as the clock outputs. Analog power supply. AVCC can be also used to bypass the PLL for test purposes. When AVC C is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
1G
9
I
2G
16
I
3G
33
I
4G FB_O UT 1Y[0:3]
40 35 2,3,6,7
I O O
2Y[0:3]
18,19,22,23
O
3Y[0:3]
26,27,30,31
O
4Y[0:3]
42,43,46,47
O
AVCC AGND VC C GND
11,38 13,14,36 1,8,17,24,25,32,41,48 4,5,10,15,20,21,28,29, 34,39,44,45
Power
Ground Analog ground. AGND provides the ground reference for the analog circuitry. Power Power supply
Ground Ground
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PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs
Absolute Maximum Ratings (Over Operating Free-Air Temperature Range, unless otherwise noted)
Symbol VCC VI VO VIK IO_DC IO_DC Power TSTG Supply voltage range Input voltage range(1) Voltage range applied to any output(1,2) Input Clamp Current Continuous output current (VO = 0 or VCC) Continuous output through VCC or ground Maximum power dissipation at TA= 55oC in still air(3) Storage temperature 65 Parame te r M in. 0.5 0.5 0.5 50 50 100 0.85 150 W
oC
M ax. 4.6 6.5 VCC + 0.5
Units
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect reliability. Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6V maximum. 3. Maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions (4)
Symbol VCC VIH VIL VI TA IOH IOL Supply voltage High level input voltage Low level input voltage Input voltage Operating free- air temperature High level output current Low level output current 0.0 0 Parame te r M in. 3.0 2.0 0.8 VCC 70 12 12 C mA M ax. 3.6 V Units
Note 4. Unused inputs must be held high or low to prevent them from floating.
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PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs
Function Table
xG L L H H
Note: x is from 1 to 4
CLK L H L H
xY [0:3] L L L H
FB_OUT L H L H
Electrical Characteristics (Over Recommended Operating Free-air Temperature Range)
Symbol VIK, Input clamp voltage VOH Te s t Condition Input current at 18mA IOH = 100A IOH = 12mA IOH = 6mA IOL = 100A VOL II, Input current Analog supply current, ICC CI CO ICC IOL = 12mA IOL = 6mA Clock input voltage = VCC or GND Clock input voltage = VCC or GND Input voltage = VCC or GND O utput voltage = VCC or GND O ne input @ VCC 0.6V, other inputs @VCC or GND VCC 3V Min. to Max. 3V Min. to Max. 3V VCC 0.2 2.1 2.4 M in. Typ. 0.79 2.99 2.66 2.83 0.01 0.3 0.15 0.2 0.8 0.55 5 12 4.0 6.0 5.0 500 4.0 A mA pF A V M ax. 1.2 Units
3.6V
3.3V 3.3V to 3.6V
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ICC (mA)
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PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs
Timing Requirements (Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature)
Symbol FCLKOP tCLKAPP tSTABLILIZATION DCYI Application clock Parame te r O perator clock frequency
(1)
M in. 25 6 40
M ax. 150 133 1 60
Units MHz ms %
frequency(2,4)
Stabilization time after power up(3) Input clock duty cycle
Notes: 1. Operating Clock Frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low-speed system debug). 2. Application Clock Frequency indicates a range over which the PLL must meet all of the timing parameters. 3. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. 4. Frequency and loading condition should not exceed 0.85 watt power dissipation (package limitation). Please refer to Graph 1.
350 300 250 200 150 100 50 0 0 50 100 150
Load = 22pF Load = 10pF
Clock Frequency (MHz)
Graph 1. Dynamic Current vs. Clock Frequency (VCC = 3.6V, TA = 25C)
Switching Characteristics
Parame te r tphase error tsk(O)(2) Jitter(pk- pk) Duty cycle tr tf
(Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature, CL = 22pF) (1,3)
From (Input) CLKIN = 100MHz Any Y or FBOUT F(CLKIN > 66MHz) F(CLKIN 66MHz) F(CLKIN > 66MHz) CLKIN = 50 to 150MHz from 20% to 80%
To (Output) FBIN
VCC = 3.3V 0.165V M in. Typ. M ax.
VCC = 3.3V 0.3V M in. 150 100 Typ. M ax. +170 200 100 55 55 2.1 2.5 45 45
Units
ps
Any Y or FBOUT 1.3 1.7 2.1 2.5
% ns
0.7 1.2
Notes: 1. These parameters are not production tested. 2. The tsk(O) specification is only valid for equal loading of all outputs. 3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
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PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs
Parameter Measurement Information
3V Input
From Output Under Test 500
50% VCC
50% VCC 0V
tpd Output 80% 20% 50% VCC 80% 20% VOH VOL
22pF
Load Circuit
tr
tf
Voltage Waveforms Propagation Delay times
Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: CLKIN 100MHz, ZO = 50 ohms, tr 1.2ns, tf 1.2ns. 3. The outputs are measured one at a time with one transition per measurement.
CLKIN
FBIN tphase error
FBOUT
Any Y tsk(O)
Any Y
Any Y tsk(O)
Phase Error and Skew Calculations
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PI6C2516 Phase-Locked Loop Clock Driver with 16 Clock Outputs
48-pin Thin Shrink Small-OutlinePackage (A)
48
.236 .244
6.0 6.2
1
.488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.0197 BSC 0.50
.007 .010 0.17 0.27
.002 .006 0.05 0.15
Ordering Information
Part Numbe r PI6C2516 Orde ring P/N PI6C2516A Package 48- pin TSSO P
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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